Abstract
The next few years will bring great changes in the way our society views the high-tech community. We're in the early stages of a transition that will result in recognition of the electronics industry as a major contributor to the resolution of the world's global warming problems. To date, companies are talking about power reduction initiatives, but more can be done. From the design of "power-smart" chips and systems to the development of industry-wide power efficiency guidelines, the new power paradigm calls for the electronics industry to take responsibility for reducing energy consumption, improving power efficiency and ultimately, reducing greenhouse gasses.
"Power" in a Changing World
In the 1990s, "power" was discussed in relation to supplying power to a system or providing volts and amps to a PC card. And, for most people, "low power" was about a few power-conscious products that looked good on paper, but often saw little success.
Power in semiconductor devices takes two basic forms: static and dynamic. Static power is consumed when the part is not doing any useful work, while dynamic power is consumed when the device is actively working. Until recently, dynamic power was the dominant source of power consumption. Once helping to manage the dynamic power problem, device supply voltages (VCC) had scaled downward with process shrinks and subsequent lower system voltages, but the days of continued scaling are gone. Additionally, the physics associated with integrated circuits (ICs) on smaller process geometries have dramatically increased power related to leakage. And, with leakage worsening, static power has begun to dominate the power consumption equation as the biggest concern (Figure 1).
Figure 1 illustrates the increasing contribution of static power at shrinking process nodes.
Figure 1: Static Power Significant at 90 nm
Another dramatic change from the 1990s is the proliferation of electronics in our society. Yesterday, we used pen and paper to interact, inform, and communicate. Today, we use electronic devices, such as the Apple iPhone® and Palm Treo™ smart phones. As the trend toward portable electronics continues, the world is less willing to buy equipment, like desktop PCs, that has to be plugged into a wall socket. Wasting nearly half of the power delivered to them and increasing the cost of power, today's desktop PCs are a perfect example of the need for low-power offerings.
Unfortunately, the generation of the electricity required to power electronic systems contributes to a surprisingly high proportion of the greenhouse gasses associated with global warming, a real and serious issue. According to a United Nations report issued in May 2007, the average global temperature will rise by as much as 11°F by the turn of the century, even with an aggressive program aimed at minimizing this rise.
As a result, companies are talking about reducing energy usage across the power continuum—from chips to systems—with the goal of helping to protect the environment. Though environmentally friendly steps have been taken, such as lead-free initiatives and RoHS compliance, the electronics industry has not adequately addressed the power issue. And, whereas the presence of small quantities of lead in electronics devices does indeed present a problem, its scope is minimal compared to the disastrous effects that could come if we fail to control global warming.
For example, it is interesting to note that no Environmental Protection Agency (EPA) Energy Star® guidelines exist for semiconductors to date. Though these semiconductor products directly contribute to the power efficiency and management of Energy Star-rated products, the industry has not yet rallied around an approach to benchmarking power efficiency for "low-power" ICs. Well-conceived requirements for semiconductors would enable boards, systems, and end products to minimize energy consumption, improve power efficiency, and reduce greenhouse gasses.
Certainly, a part of the solution to the problem lies in the hands of the electronics industry. With today's power-smart technologies, more can be done. Taking responsibility is mandatory—no longer a choice. The new "power" means a coordinated attack on power consumption—from chips to systems.
Power-Smart Chips
Designers of portable, battery-powered equipment are faced with a daunting challenge—insatiable consumer demand for smaller, cheaper, feature-rich portable devices with longer battery lives, lower cost, and short time to market. The longer the battery life, the lower the cost of ownership for consumers. If the battery life of a smart phone is good for six hours, and if lithium ion batteries typically support 300–500 recharge cycles before a "costly" battery replacement is required, would not these devices be even more attractive if the battery life was extended beyond six hours to weeks or months?
Designers have traditionally relied on application-specific integrated circuits (ASICs) to support the low power consumption that portable designers require. But ASICs come with their own baggage, namely expensive mask sets and longer time to market. Alternatively, programmable logic solutions, particularly those based on SRAM technology, have provided the shortened time to market but with inherently high static power consumption. In fact, some of today's "low-power" field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) draw upwards of 30 mA, which is often an order of magnitude or two higher than typical battery-operated applications can tolerate.
SRAM-based devices also experience power surges at startup that can cause battery drain or possible system-initialization failures. Compounding the issue further, each process node shrink means additional static power consumption for transistor-heavy, SRAM-based FPGAs. This is due to worsening problems like quantum tunneling and sub-threshold leakage, which create real challenges for devices targeted to portable applications. The power problem becomes further confused when considering new SRAM-based solutions that utilize flash technology to program the chip's SRAM architecture. Though marketed as flash-based devices, these solutions must add additional circuitry to the already power-hungry SRAM FPGA fabric.
Fortunately, "true flash" programmable logic technologies exist. Because nonvolatile, flash-based FPGAs do not use millions of power-hungry SRAM configuration bit cells, they have significantly lower static power than SRAM-based solutions, making them ideal for low-power applications. In fact, some available flashbased FPGAs have been designed expressly for low-power applications. With static power as low as 5 µW, these FPGAs deliver more complexity and features with four times lower static power and as much as five times longer battery life in portable applications than CPLDs.
Compared with today's "low-power" best-of-breed, SRAM-based FPGAs, Actel's flash-based IGLOO™ FPGAs deliver between 100 and 1,000 times improvement in power reduction. The two to three orders of magnitude lower static power consumption can translate into weeks and months of standby battery life. For designers of battery-operated portable applications, other advantages of flash-based devices include flexible power saving modes with rapid recovery to operation, low dynamic power consumption, and clock management.
Power-smart chips can offer more than low-power consumption. They also can be used to intelligently control and reduce total power consumption in the overall system. For example, the mixed-signal Actel Fusion™ Programmable System Chip (PSC) offers the integration of FPGA logic with other elements used in system management, such as flash, analog, microprocessors, and clock management. This integration enables designers to remove parts from the board, reduce total power consumption and bill-of-materials (BOM) costs, and enable sophisticated power management of the system.
Power-Smart Systems
Generally, when designing a system, a power goal is set. Often, however, if the designer "approximately" meets this specification, little additional effort is expended to improve the design, leaving watts on the table. Because electronic systems are sold by the hundreds of millions, a few watts of inefficiency in each system eventually translates into staggering amounts of resources being consumed unnecessarily, which ultimately has a detrimental impact on the environmental. Unfortunately, there is usually no easy way to track power down to the individual components or voltage rails, making the job of removing all unnecessary power from devices a difficult task. There is also rarely a way to measure voltages, currents, and temperatures when the system is in operation, which complicates the ability to recognize when things are going badly.
The proliferation of new standards, such as Advanced Telecommunications Computer Architecture (ATCA), MicroTCA, and Intelligent Platform Management Interface (IPMI), prove that the world needs and wants system and enterprise-level power management. These applications require the ability to measure voltages, currents, and temperature in real time and recognize problems; the ability to log and communicate this data; and the ability to take corrective action when appropriate. After all, knowing that a power supply is providing more current than it should or that the board temperature is higher than it should be is not helpful unless steps can be taken to correct it.
System management has historically required multi-chip solutions. With as many as 10–15 extra chips, these designs cost money, consume valuable board space, and burn additional power, which means that the "solution" to the problem is not a solution at all. Multi-chip solutions also require substantial engineering resources, which are often a scarce commodity. And yet, despite these significant costs, the industry has put little effort forth into being smarter about managing and controlling system power.
Recognizing that "one-size-fits-all" is one of the world's greatest lies, it seems clear that a field programmable solution is called for. A flash-based, single-chip, field-programmable device implementation is the best approach for creating a simple and inexpensive system management solution. Already available off the shelf, these live-at-power-up solutions reduce component count and enable system power management. Because they are field-programmable, these flexible devices also allow the easy adaptation to the unique needs and changing demands of the project, the system, the board, and the engineer. Further reducing engineering resource requirements, Actel’s nonvolatile, mixed-signal Fusion PSCs are complete solutions and include both software and hardware.
Additionally, by integrating necessary housekeeping functions, such as boot up and power supply sequencing, with the power management functionality, system costs are improved. Building power-smart systems costs less upfront and saves significant operating costs. Since each watt that is saved reduces system operating costs by one to two dollars per year, the deployment of cost-effective power management solutions at the enterprise level can save staggering amounts of energy, huge amounts of money, and, more importantly, reap significant benefits on our environment.
A Power-Smart Example
Today, electric motors are used in nearly everything—from elevators to home appliances. In 2005, the US consumed 4,055 billion kWh of electrical power. More than 50 percent of this power was used in electric motors, translating into a staggering 2000 billion kWh. Unfortunately, many of the motors currently in use are inefficient and waste a substantial amount of the power they consume.
With technology improvements in semiconductor processes and integration, mixed-signal FPGAs are emerging as an important alternative for motor control implementation. These highly integrated, flexible platforms offer the bulk of the resources needed for motor control on a single, low-cost device. Using FPGAs in lieu of fixed logic gives designers the flexibility to implement the most efficient design for their application, and the ability to use the same device across a range of motor applications.
The efficiency of small AC motors can be as low as 50 percent. While motor efficiency improves to more than 90 percent as motor size increases, there is still opportunity to improve efficiency and reduce energy consumption. By adding intelligent load matching or variable speed control, the power efficiency of electricmotors across the full range can be increased. With a reprogrammable, mixed-signal FPGA and a soft optimized microprocessor, such as the ARM7™ or the ARM® Cortex-M1 processor, this can be accomplished for a range of motor types at a cost attractive for most applications. In fact, coupled with best practices, this combination can result in motor efficiencies approaching 95 percent and, when implemented broadly, could result in annual reduction in U.S. energy consumption of as much as 300 billion kWh, saving billions of dollars and reducing greenhouse gasses by more than 180 million metric tons.
The combination of a reprogrammable, mixed-signal solution and an ARM Cortex-M1 soft microprocessor can improve motor efficiencies, reduce energy consumption, save billions of dollars, and minimize greenhouse gas emissions (Figure 2).
Figure 2: Power Savings from AC Motor Control Using Mixed-Signal FPGAs
Conclusion
Over the last two decades, the concept of power has greatly changed. Simultaneously, different types of electronic systems have proliferated. Tragically, the generation of the electricity required to power these electronic systems contributes to a surprisingly high fraction of the greenhouse gasses associated with global warming.
Though companies are talking about reducing energy usage to help protect the environment, more can be done. Whether the design of power-smart chips and systems or the development of industry-wide power efficiency guidelines, the new power paradigm calls for the electronics industry to take responsibility for reducing energy consumption, improving power efficiency and ultimately, reducing greenhouse gasses.
November 29, 2007
2007年11月29日 星期四
2007年11月27日 星期二
Actel 推出業界首款用於可編程邏輯器件的4x4 mm封裝
(技術新聞, 11 月 23 日 2007 年)
Actel公司宣佈為其低功耗5µW IGLOO現場可編程閘陣列 (FGPA) 推出焊球間距僅為0.4mm的4mm封裝，是目前市場上體積最小的可編程邏輯器件封裝，為業界發展奠下了重要的里程碑。全新封裝的Actel器件與其現有小型8x8 mm 和 5x5 mm封裝相輔相成，與其它競爭的可編程邏輯產品相比，新封裝器件可為設計人員帶來4倍更高的密度、3倍更多的I/O，以及減小尺寸達36%。這款新的IGLOO FPGA比玉米粒還要小，是智慧型電話、可攜式媒體播放機、安全行動通信設備、遙控感測器、保安鏡頭和可攜式醫療設備等功耗敏感及空間受限的掌上型設備的理想解決方案。Actel公司董事總經理兼總裁 John East表示：“今天，設計人員需要小型封裝的超低功耗器件、功率最佳化的設計工具，以及相輔相成的IP解決方案以創建成功的可攜式應用。Actel將針對這些領域而繼續進行研發創新，為可編程設計邏輯器件行業建立新的標準。隨著Actel不斷向前發展，我們將繼續致力於解決可攜式產品設計人員所面臨的獨特挑戰，尤其是在功率效率和功率管理所需的輔助性技術方面。我們期望一提到功耗時，設計人員就會立即想到Actel。”4x4封裝系列的首款器件是30,000門的IGLOO AGL030。較之於其它競爭產品，這款IGLOO FPGA的靜態功耗只是其二百分之一，而電池壽命可延長超過10倍。此外，Actel還提供採用接腳相容8x8 mm 及 5x5 mm封裝功能豐富的IGLOO系列器件，可以實現封裝之間的移植。4x4mm器件帶有板上 快閃記憶體、66個使用者I/O和超過192個等效巨集單元。IGLOO支援獨有的低功耗狀態，如Actel的創新Flash*Freeze模式，能夠停止時鐘，讓I/O進入已知狀態，並大大降低功耗，又同時保存SRAM和寄存器的狀態。在單個引腳的控制下，IGLOO器件能在1μs之內進入或退出Flash*Freeze模式，從而迅速及簡便地實現系統的大幅節能。價格及供貨採用4x4 mm 封裝的IGLOO AGL030器件將於12月提供樣品，並計畫於2008年第一季投入量產。
Actel公司宣佈為其低功耗5µW IGLOO現場可編程閘陣列 (FGPA) 推出焊球間距僅為0.4mm的4mm封裝，是目前市場上體積最小的可編程邏輯器件封裝，為業界發展奠下了重要的里程碑。全新封裝的Actel器件與其現有小型8x8 mm 和 5x5 mm封裝相輔相成，與其它競爭的可編程邏輯產品相比，新封裝器件可為設計人員帶來4倍更高的密度、3倍更多的I/O，以及減小尺寸達36%。這款新的IGLOO FPGA比玉米粒還要小，是智慧型電話、可攜式媒體播放機、安全行動通信設備、遙控感測器、保安鏡頭和可攜式醫療設備等功耗敏感及空間受限的掌上型設備的理想解決方案。Actel公司董事總經理兼總裁 John East表示：“今天，設計人員需要小型封裝的超低功耗器件、功率最佳化的設計工具，以及相輔相成的IP解決方案以創建成功的可攜式應用。Actel將針對這些領域而繼續進行研發創新，為可編程設計邏輯器件行業建立新的標準。隨著Actel不斷向前發展，我們將繼續致力於解決可攜式產品設計人員所面臨的獨特挑戰，尤其是在功率效率和功率管理所需的輔助性技術方面。我們期望一提到功耗時，設計人員就會立即想到Actel。”4x4封裝系列的首款器件是30,000門的IGLOO AGL030。較之於其它競爭產品，這款IGLOO FPGA的靜態功耗只是其二百分之一，而電池壽命可延長超過10倍。此外，Actel還提供採用接腳相容8x8 mm 及 5x5 mm封裝功能豐富的IGLOO系列器件，可以實現封裝之間的移植。4x4mm器件帶有板上 快閃記憶體、66個使用者I/O和超過192個等效巨集單元。IGLOO支援獨有的低功耗狀態，如Actel的創新Flash*Freeze模式，能夠停止時鐘，讓I/O進入已知狀態，並大大降低功耗，又同時保存SRAM和寄存器的狀態。在單個引腳的控制下，IGLOO器件能在1μs之內進入或退出Flash*Freeze模式，從而迅速及簡便地實現系統的大幅節能。價格及供貨採用4x4 mm 封裝的IGLOO AGL030器件將於12月提供樣品，並計畫於2008年第一季投入量產。
Actel將FPGA應用延伸至Airbus商用客機
Actel日前表示，其現場可編程閘陣列(FPGA)和矽智財權(IP)核心模組已開始應用在Airbus A380商用客機中。據表示，目前Actel共有超過700個ProASIC Plus和SX-A FPGA被設計到飛行電腦；引擎控制和監控；煞車系統；安全警報系統；機艙空氣調節及增壓；以及駕駛員座艙顯示等應用中。
此外，Actel的Core10/100 IP模組、乙太網路媒體存取控制器和ProASIC Plus FPGA也被應用在A380客機的Avionics Full-Duplex Switched Ethernet (AFDX)通信鏈路中。A380甫於4月完成試飛，Actel表示，其元件將有助於A380實現於2006年前開始運載乘客的服務目標。
Actel以Flash為基礎的ProASIC Plus元件是單晶片的通電即行解決方案，具有高性能和低功耗特性，再結合非揮發性和系統內可編程功能。以反熔絲為基礎的SX-A系列FPGA是高度安全的單晶片解決方案，兼具高速度和低功耗特性。
與以SRAM為基礎的FPGA不同，Actel的ProASIC Plus和SX-A元件具有免除因來自太空之中子引起的韌體錯誤之免疫能力，並且無需特殊之減緩輻射技術。當來自太空之高能量中子進入SRAM FPGA用於配置的SRAM儲存單元時，極有可能會引起功能故障，造成元件以不可預知的方式運作。這對於航空應用而言，是非常不利的。
Core10/100 IP模組支援10/100Mbps全雙工和半雙工運作。在Airbus A380中，IP核心被使用在引擎控制監控下翼(down-wing)應用的AFDX通信鏈路。這項富挑戰性的應用需要嚴格的溫度性能和韌體錯誤抵抗性。Actel的ProASIC Plus FPGA和Core10/100 IP模組可提供可靠的高性能解決方案，並且具有保證服務。
此外，Actel的Core10/100 IP模組、乙太網路媒體存取控制器和ProASIC Plus FPGA也被應用在A380客機的Avionics Full-Duplex Switched Ethernet (AFDX)通信鏈路中。A380甫於4月完成試飛，Actel表示，其元件將有助於A380實現於2006年前開始運載乘客的服務目標。
Actel以Flash為基礎的ProASIC Plus元件是單晶片的通電即行解決方案，具有高性能和低功耗特性，再結合非揮發性和系統內可編程功能。以反熔絲為基礎的SX-A系列FPGA是高度安全的單晶片解決方案，兼具高速度和低功耗特性。
與以SRAM為基礎的FPGA不同，Actel的ProASIC Plus和SX-A元件具有免除因來自太空之中子引起的韌體錯誤之免疫能力，並且無需特殊之減緩輻射技術。當來自太空之高能量中子進入SRAM FPGA用於配置的SRAM儲存單元時，極有可能會引起功能故障，造成元件以不可預知的方式運作。這對於航空應用而言，是非常不利的。
Core10/100 IP模組支援10/100Mbps全雙工和半雙工運作。在Airbus A380中，IP核心被使用在引擎控制監控下翼(down-wing)應用的AFDX通信鏈路。這項富挑戰性的應用需要嚴格的溫度性能和韌體錯誤抵抗性。Actel的ProASIC Plus FPGA和Core10/100 IP模組可提供可靠的高性能解決方案，並且具有保證服務。
2007年11月26日 星期一
明導科技與MathWorks聯手進行FPGA設計
【日經BP社報導】 美國明導科技（Mentor Graphics Corp.）與美國The MathWorks在FPGA設計領域展開了合作（英文發佈資料）。 合作的具體內容是確認MathWorks的“Simulink HDL Coder”輸出的HDL代碼可輸入到明導科技的FPGA用邏輯合成工具“Precision Synthesis”中去，併為此開發了組合兩產品的工藝流程。Simulink HDL Coder是MathWorks開發的信號處理系統設計驗證工具“Simulink”的選項功能，可將Simulink的設計結果以週期精確級（Cycle Accurate）轉變為可進行邏輯合成的RTL Verilog-HDL HDL代碼。另外，支援此次設計流程的Precision Synthesis為2006a之後的版本。（記者：小島 郁太郎）
Mentor Graphics Announces an Optimized FPGA Design Flow Between Precision Synthesis and MathWorks Simulink HDL Coder
WILSONVILLE, Ore., November 15, 2007 – Mentor Graphics Corporation (NASDAQ: MENT) today announced support for hardware description language (HDL) generated by MathWorks Simulink HDL Coder in the Mentor Graphics Precision® suite of advanced synthesis products. This capability enables mutual customers to transfer VHDL and Verilog generated by Simulink HDL Coder into the Precision Synthesis tool directly to generate an optimized netlist implementation for field programmable gate array (FPGA) designs. All mutual customers using Precision 2006a release or newer with Simulink HDL Coder can benefit from this flow, which will improve the productivity of FPGA design synthesis.
The MathWorks and Mentor Graphics have collaborated on this flow to assure interoperability. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB code, and Stateflow charts.
「Simulink HDL Coder and Precision Synthesis provide a rapid path from Simulink models to FPGA implementation,」 said Ken Karnofsky, director of marketing, Signal Processing and Communications for MathWorks. 「We are pleased to offer a workflow that leverages the capabilities of Mentor's advanced FPGA synthesis products.」
「This integrated flow with Simulink HDL Coder and Precision Synthesis benefits our mutual customers,」 said Daniel Platzker, product line director of FPGA Synthesis at Mentor Graphics Design Creation and Synthesis division. 「Both are industry-leading tools that support a vendor-independent design methodology, and this integrated flow significantly shortens the time-to-market of FPGA designs.」
Precision Synthesis: The Centerpiece of Mentor Graphics FPGA Flow The Precision Synthesis tool is the industry's most comprehensive vendor-independent solution for FPGA design, and it is the only synthesis tool which offers true push button multi-vendor physical synthesis. With comprehensive language support, including SystemVerilog, an advanced ASIC prototyping flow, and automatic incremental synthesis, the Precision Synthesis tool is uniquely suited to handle today's high-end FPGAs designs. The Precision Synthesis tool features award-winning design analysis, allowing designers to cross-probe between multiple views and perform interactive static timing "what-if" analyses. The Precision Synthesis tool reduces design iterations and enables faster, more predictable completion of designs, while delivering a high quality of results.
Precision Synthesis is available at a starting price of $20,200 (USD). For additional product information, go to the company website: http://www.mentor.com/fpga , contact a local Mentor Graphics sales office, or call 1-800-547-3000 for specific product and pricing details.
About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Precision are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
Mentor Graphics Announces an Optimized FPGA Design Flow Between Precision Synthesis and MathWorks Simulink HDL Coder
WILSONVILLE, Ore., November 15, 2007 – Mentor Graphics Corporation (NASDAQ: MENT) today announced support for hardware description language (HDL) generated by MathWorks Simulink HDL Coder in the Mentor Graphics Precision® suite of advanced synthesis products. This capability enables mutual customers to transfer VHDL and Verilog generated by Simulink HDL Coder into the Precision Synthesis tool directly to generate an optimized netlist implementation for field programmable gate array (FPGA) designs. All mutual customers using Precision 2006a release or newer with Simulink HDL Coder can benefit from this flow, which will improve the productivity of FPGA design synthesis.
The MathWorks and Mentor Graphics have collaborated on this flow to assure interoperability. Simulink HDL Coder generates bit-true, cycle-accurate, synthesizable Verilog and VHDL code from Simulink models, Embedded MATLAB code, and Stateflow charts.
「Simulink HDL Coder and Precision Synthesis provide a rapid path from Simulink models to FPGA implementation,」 said Ken Karnofsky, director of marketing, Signal Processing and Communications for MathWorks. 「We are pleased to offer a workflow that leverages the capabilities of Mentor's advanced FPGA synthesis products.」
「This integrated flow with Simulink HDL Coder and Precision Synthesis benefits our mutual customers,」 said Daniel Platzker, product line director of FPGA Synthesis at Mentor Graphics Design Creation and Synthesis division. 「Both are industry-leading tools that support a vendor-independent design methodology, and this integrated flow significantly shortens the time-to-market of FPGA designs.」
Precision Synthesis: The Centerpiece of Mentor Graphics FPGA Flow The Precision Synthesis tool is the industry's most comprehensive vendor-independent solution for FPGA design, and it is the only synthesis tool which offers true push button multi-vendor physical synthesis. With comprehensive language support, including SystemVerilog, an advanced ASIC prototyping flow, and automatic incremental synthesis, the Precision Synthesis tool is uniquely suited to handle today's high-end FPGAs designs. The Precision Synthesis tool features award-winning design analysis, allowing designers to cross-probe between multiple views and perform interactive static timing "what-if" analyses. The Precision Synthesis tool reduces design iterations and enables faster, more predictable completion of designs, while delivering a high quality of results.
Precision Synthesis is available at a starting price of $20,200 (USD). For additional product information, go to the company website: http://www.mentor.com/fpga , contact a local Mentor Graphics sales office, or call 1-800-547-3000 for specific product and pricing details.
About Mentor Graphics Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $825 million and employs approximately 4,300 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
Mentor Graphics and Precision are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
Actel推4×4mm封裝IGLOO FPGA
Actel推4×4mm封裝IGLOO FPGA上網時間 : 2007年11月26日
Actel宣佈為其低功耗5μW IGLOO現場可程式閘陣列(FGPA)，推出焊球間距僅為0.4mm的4mm封裝產品。全新封裝的Actel元件與其現有小型8×8mm和5×5mm封裝相輔相成，號稱可為設計人員帶來高4倍的密度、3倍的I/O，以及減少尺寸達36%。
新款IGLOO FPGA尺寸號稱比玉米粒還要小，適合智慧手機、可攜式媒體播放器、安全行動通訊設備、遙控感測器、保全鏡頭和可攜式醫療設備等，對功耗敏感及電路空間有限的手持式設備應用。首款4×4封裝系列元件是3萬閘的IGLOO AGL030；Actel表示，這款IGLOO FPGA的靜態功耗極低，可延長電池壽命超過10倍。
此外，Actel還提供採用接腳相容8×8mm及5×5mm封裝的IGLOO系列元件，可以實現封裝之間的移植。4×4mm元件支援板上 Flash記憶體、66個用戶I/O和超過192個的等效宏單元。IGLOO支援獨有的低功耗狀態，比如Actel的創新Flash*Freeze模式，能夠停止時脈，讓I/O進入已知狀態，顯著降低功耗，同時保存SRAM和暫存器的現有狀態。
在單個接腳的控制之下，IGLOO元件能在1μs之內進入或退出Flash*Freeze模式，因而迅速及簡便地實現系統的大幅節能。採用4×4mm封裝的IGLOO AGL030元件將於12月提供樣品，計劃於2008年第一季投入量產。
Actel宣佈為其低功耗5μW IGLOO現場可程式閘陣列(FGPA)，推出焊球間距僅為0.4mm的4mm封裝產品。全新封裝的Actel元件與其現有小型8×8mm和5×5mm封裝相輔相成，號稱可為設計人員帶來高4倍的密度、3倍的I/O，以及減少尺寸達36%。
新款IGLOO FPGA尺寸號稱比玉米粒還要小，適合智慧手機、可攜式媒體播放器、安全行動通訊設備、遙控感測器、保全鏡頭和可攜式醫療設備等，對功耗敏感及電路空間有限的手持式設備應用。首款4×4封裝系列元件是3萬閘的IGLOO AGL030；Actel表示，這款IGLOO FPGA的靜態功耗極低，可延長電池壽命超過10倍。
此外，Actel還提供採用接腳相容8×8mm及5×5mm封裝的IGLOO系列元件，可以實現封裝之間的移植。4×4mm元件支援板上 Flash記憶體、66個用戶I/O和超過192個的等效宏單元。IGLOO支援獨有的低功耗狀態，比如Actel的創新Flash*Freeze模式，能夠停止時脈，讓I/O進入已知狀態，顯著降低功耗，同時保存SRAM和暫存器的現有狀態。
在單個接腳的控制之下，IGLOO元件能在1μs之內進入或退出Flash*Freeze模式，因而迅速及簡便地實現系統的大幅節能。採用4×4mm封裝的IGLOO AGL030元件將於12月提供樣品，計劃於2008年第一季投入量產。
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