Cadence, Mentor launch Open Verification Methodology

A result of their joint efforts to unify the SystemVerilog method, Cadence Design Systems Inc. and Mentor Graphics Corp. has launched the Open Verification Methodology (OVM).

Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge from www.ovmworld.org. The OVM Web site is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions and future plans.

The OVM, based on IEEE Std. 1800-2005 SystemVerilog standard, is the first open, language interoperable, SystemVerilog verification methodology in the industry. The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.

As a joint development initiative between Mentor Graphics and Cadence Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers.

The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments. It easily integrates plug-and-play VIP and ensures code portability and reuse.

"The OVM represents a major step forward in protecting our customers' investment in verification flows and reusable VIP," said Robert Hum, VP and general manager of Mentor's verification and test business unit. "After extensive customer interaction, we believe OVM will definitely accelerate the move to SystemVerilog, and provide significant competitive advantage to design and verification teams around the world."

"We have discussed OVM with more than a thousand engineers at customer sites and have worked with more than a dozen customers and partners during the beta period," said Ziv Binyamini, corporate VP, product and technologies organization at Cadence. "The level of interest in OVM is overwhelming, so we are pleased to be able to make it available to the entire industry as a critical step in delivering on the full promise of SystemVerilog."